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1 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms features ? jedec pinout in a 100-pin, dual in-line memory module (dimm) ? 4mb (1 meg x 32) and 8mb (2 meg x 32) ? utilizes 100 mhz and 125 mhz sdram components ? single +3.3v 0.3v power supply ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8 or full page ? auto precharge and auto refresh modes ? self refresh mode ? 64ms, 4,096-cycle refresh ? lvttl-compatible inputs and outputs ? serial presence-detect (spd) options marking ? package 100-pin dimm (gold) g ? timing 8ns cycle (125 mhz clock rate) -8 10ns cycle ( 100 mhz clock rate) -10 pin assignment (front view) 100-pin dimm (h-3; 4mb) (h-4; 8mb) pin front pin front pin back pin back 1v ss 26 v ss 51 v ss 76 v ss 2 dq0 27 cke0 52 dq8 77 nc/ cke1* 3 dq1 28 we# 53 dq9 78 dnu 4 dq2 29 s0# 54 dq10 79 nc/s1#* 5 dq3 30 s2# 55 dq11 80 nc/s3#* 6v dd 31 v dd 56 v dd 81 v dd 7 dq4 32 nc 57 dq12 82 nc 8 dq5 33 nc 58 dq13 83 nc 9 dq6 34 nc 59 dq14 84 nc 10 dq7 35 nc 60 dq15 85 nc 11 dqmb0# 36 v ss 61 dqmb1# 86 v ss 12 v ss 37 dqmb2# 62 v ss 87 dqmb3# 13 a0 38 dq16 63 a1 88 dq24 14 a2 39 dq17 64 a3 89 dq25 15 a4 40 dq18 65 a5 90 dq26 16 a6 41 dq19 66 a7 91 dq27 17 a8 42 v dd 67 a9 92 v dd 18 a10 43 dq20 68 ba0 93 dq28 19 nc 44 dq21 69 nc 94 dq29 20 nc 45 dq22 70 nc 95 dq30 21 v dd 46 dq23 71 v dd 96 dq31 22 dnu 47 v ss 72 ras# 97 v ss 23 rfu 48 sda 73 cas# 98 sa0 24 rfu 49 scl 74 rfu 99 sa1 25 ck0 50 v dd 75 nc/ck1* 100 sa2 *8mb version only synchronous dram module mt2lsdt132u, mt4lsdt232ud for the latest data sheet, please refer to the micron web site: www.micron.com/mti/msp/html/datasheet.html key sdram component timing parameters speed clock access time setup hold grade frequency cl = 2* cl = 3* time time -8 125 mhz 9ns 6ns 2ns 1ns -10 100 mhz 9ns 7.5ns 3ns 1ns *cl = cas (read) latency part numbers part number configuration device package mt2lsdt132ug-8_ 1 meg x 32 tsop mt2lsdt132ug-10_ 1 meg x 32 tsop mt4lsdt232udg-8_ 2 meg x 32 tsop mt4lsdt232udg-10_ 2 meg x 32 tsop general description the mt2lsdt132u and mt4lsdt232ud are high-speed cmos, dynamic random-access, 4mb and 8mb memories organized in a x32 configuration. these modules use sdrams that are internally configured as dual memory arrays with a synchronous interface (all signals are regis- tered on the positive edge of the clock signal ck0). read and write accesses to the sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed note : all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt2lsdt132ug-10 c1. micron is a registered trademark of micron technology, inc.
2 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms general description (continued) sdram modules offer substantial advances in dram operating performance, including the ability to synchro- nously burst data at a high data rate with automatic column- address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram operation, refer to the 16mb: x16 sdram data sheet. serial presence-detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and tim- ing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimms scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/ eeprom addresses. sequence. accesses begin with the registration of an ac- tive command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 selects the bank; a0-a10 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the modules provide for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the modules use an internal pipelined architecture to achieve high- speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing the alternate bank will hide the precharge cycles and provide seamless, high-speed, random-access operation. the modules are designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible.
3 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms functional block diagram mt2lsdt132u (4mb) note : 1. all resistor values are 10 ohms. 2. reference desi g nators in this dia g ram do not necessaril y match the actual module. a0 spd scl sda a1 a2 sa0 sa1 sa2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 we# ras#: sdrams u0-u1 cas#: sdrams u0-u1 cke: sdrams u0-u1 we#: sdrams u0-u1 a0-a10: sdrams u0-u1 ba0: sdrams u0-u1 a0-a10 ba0 v dd v ss sdrams u0-u1 sdrams u0-u1 ck0 u0 u1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb1 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb3 s2# ck1 10pf 6.8pf u0-u1 = mt48lc1m16a1tg sdrams
4 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms functional block diagram mt4lsdt232ud (8mb) a0 spd scl sda a1 a2 sa0 sa1 sa2 dqmh u0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 cke1 we# ras#: sdrams u0-u3 cas#: sdrams u0-u3 cke: sdrams u0-u1 cke: sdrams u2-u3 we#: sdrams u0-u3 a0-a10: sdrams u0-u3 ba0: sdrams u0-u3 a0-a10 ba0 v dd v ss sdrams u0-u3 sdrams u0-u3 ck0 u0 u1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb1 dqmh u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# s1# dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 s2# dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb3 dqmh u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# s3# ck1 u2 u3 note : 1. all resistor values are 10 ohms. 2. reference desi g nators in this dia g ram do not necessaril y match the actual module. dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 6.8pf 6.8pf u0-u3 = mt48lc1m16a1tg sdrams
5 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms pin descriptions pin numbers symbol type description 72, 73, 28 ras#, cas#, we# input command inputs: ras#, cas# and we# (along with s0#- s3#) define the command being entered. 25, 75 ck0-ck1 input clock: ck0-ck1 are driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. pin 75 is a no connect on the 4mb version. 27, 77 cke0-cke1 input clock enable: cke0 and cke1 activate (high) and deactivate (low) the ck signal. deactivating the clock provides power-down and self refresh operation (all banks idle) or clock suspend operation (burst access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including ck0-ck1, are disabled during power-down and self refresh modes, providing low standby power. pin 77 is a no connect on the 4mb version. 29, 30, 79, 80 s0#-s3# input chip select: s0#-s3# enable (registered low) and disable (registered high) the command decoder. all commands are masked when s0#-s3# are registered high. s0#-s3# are considered part of the command code. pins 79 and 80 are no connects on the 4mb version. 11, 37, 61, 87 dqmb0-dqmb3 input input/output mask: dqmb is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (after a two-clock latency) when dqmb is sampled high during a read cycle. 68 ba0 input bank address: ba0 defines to which bank the active, read, write or precharge command is being applied. ba0 is also used to program the twelfth bit of the mode register. 13-18, 63-67 a0-a10 input address inputs: a0-a10 are sampled during the active command (row-address a0-a10) and read/write command (column-address a0-a7, with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if both banks are to be precharged (a10 high). the address inputs also provide the op-code during a load mode register command. 49 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 98-100 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device.
6 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms pin descriptions (continued) pin numbers symbol type description 2-5, 7-10, 38-41, 43-46, dq0-dq31 input/output data i/os: data bus. 52-55, 57-60, 88-91, 93-96 48 sda input/output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 6, 21, 31, 42, 50, v dd supply power supply: +3.3v 0.3v. 56, 71, 81, 92 1, 12, 26, 36, 47, v ss supply ground. 51, 62, 76, 86, 97 23, 24, 74 rfu C reserved for future use: these pins should be left unconnected. 22, 78 dnu C do not use: these pins are not connected on these modules but are assigned pins on the compatible dram version.
7 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the spd device will respond with an ac- knowledge after the receipt of each subsequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. figure 3 acknowledge response from receiver scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 2 definition of start and stop scl sda start bit stop bit figure 1 data validity scl sda data stable data stable data change
8 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms note: 1. 1/0: serial data, driven to high/driven to low. serial presence-detect matrix byte description entry (version) symbol bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 0 number of bytes used by micron 128 10000000 80 1 total number of spd memory bytes 256 00001000 08 2 memory type sdram 00000100 04 3 number of row addresses 11 00001011 0b 4 number of column addresses 8 00001000 08 5 number of banks 1 (4mb) 00000001 01 2 (8mb) 00000010 02 6 module data width 32 00100000 20 7 module data width (continued) 0 00000000 00 8 module voltage interface levels lvttl 00000001 01 9 sdram cycle time 8 (-8) t ck 10000000 80 (cas latency= 3) 10 (-10) 10100001 a0 10 sdram access from clock 6 (-8) t ac 01100000 60 (cas latency= 3) 7.5 (-10) 01110101 75 11 module configuration type nonparity 00000000 00 12 refresh rate/type 15.6 m s/self 10000000 80 13 sdram width (primary sdram) 16 00010000 10 14 error-checking sdram data width none 00000000 00 15 min. clock delay from back-to-back 1 t ccd 00000001 01 random column addresses 16 burst lengths supported 1, 2, 4, 8, page 10001111 8f 17 number of banks on sdram device 2 00000010 02 18 cas latencies supported 1, 2, 3 00000111 07 19 cs latency 0 00000001 01 20 we latency 0 00000001 01 21 sdram module attributes unbuffered 00000000 00 22 sdram device attributes: general 0e 00001110 0e 23 sdram cycle time 13 (-8) t ck 11010000do (cas latency = 2) 15 (-10) 11110000 fo 24 sdram access from clk 9 t ac 10010000 90 (cas latency = 2) 25 sdram cycle time 25 (-8) t ck 01100100 64 (cas latency = 1) 30 (-10) 01111000 78 26 sdram access from clk 22 (-8) t ac 01011000 58 (cas latency = 1) 27 (-10) 01101100 6c 27 minimum row precharge time 24 (-8) t rp 00011000 18 30 (-10) 00011110 1e 28 minimum row active to row active 16 t rrd00010000 10 29 minimum ras# to cas# delay 24 (-8) t rcd 00011000 18 30 (-10) 00011110 1e 30 minimum ras# pulse width 48 (-8) t ras 00110000 30 60 (-10) 00111100 3c 31 module bank density 4mb 00000001 01 32 command/address setup 2 (-8) t as, t cms00100000 20 3 (-10) 00110000 30
9 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms serial presence-detect (contined) byte description entry (version) symbol bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 33 command/address hold 1 t ah, t cmh00010000 10 34 data signal input setup 2 (-8) t ds 00100000 20 3 (-10) 00110000 30 35 data signal input hold 1 t dh 00010000 10 36-61 reserved bytes C 00000000 00 62 spd revision rev. 2 00000010 02 63 checksum for bytes 0-62 4mb (-8) 11001001 c9 4mb (-10) 01111110 7e 8mb (-8) 11001010 ca 8mb (-10) 01111111 7f 64 manufacturer's jedec id code micron 00101100 2c 65-71 manufacturer's jedec code (cont.) 11111111 ff 72 manufacturing location 00000001 01 00000010 02 00000011 03 00000100 04 00000101 05 00000110 06 73-90 module part number (ascii) xxxxxxxx xx 91 pcb identification code 1 00000001 01 2 00000010 02 3 00000011 03 4 00000100 04 92 identification code (cont.) 0 00000000 00 93 year of manufacture in bcd xxxxxxxx xx 94 week of manufacture in bcd xxxxxxxx xx 95-98 module serial number xxxxxxxx xx 99-127 manufacturer-specific data (rsvd) CCCCCCCC C note: 1. 1/0: serial data, driven to high/driven to low. 2. x = variable data.
10 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms commands truth table 1 provides a general reference of available commands. for a more detailed description of commands and operations, refer to the 16mb: x16 sdram data sheet. note: 1. cke is high for all commands shown except self refresh. 2. a0-a10 and ba0 define the op-code written to the mode register. 3. a0-a10 provide row address and ba0 determines which bank is made active (ba0 low = bank 0; ba0 high = bank 1). 4. a0-a7 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0 determines which bank is being read from or written to (ba0 low = bank 0; ba0 high = bank 1). 5. a10 low: ba0 determines which bank is being precharged (ba0 low = bank 0; ba0 high = bank 1). a10 high: both banks are precharged and ba0 is dont care. 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). truth table 1 C commands and dqmb operation (notes: 1) name (function) cs# ras# cas# we# dqmb addr dqs notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h l/h 8 bank/col x 4 write (select bank and column, and start write burst) l h l l l/h 8 bank/col valid 4 burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x op-code x 2 write enable/output enable CCCCl C active 8 write inhibit/output high-z CCCCh C high-z 8
11 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms note: 1. for a burst length of two, a1-a7 select the block-of- two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2-a7 select the block-of- four burst; a0-a1 select the starting column within the block. 3. for a burst length of eight, a3-a7 select the block-of- eight burst; a0-a2 select the starting column within the block. 4. for a full-page burst, the full row is selected, and a0-a7 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0-a7 select the unique column to be accessed, and mode register bit m3 is ignored. table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a7 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (256) (location 0-255) cn - 1, cn m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved m6 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 ba 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices. figure 1 mode register definition
12 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms absolute maximum ratings* voltage on v dd supply relative to v ss .......... -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ................................................ -1v to +4.6v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +125 c power dissipation ............................................................. 4w *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 6) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 24 input low voltage: logic 0; all inputs v il -0.5 0.8 v 24 input leakage current: we#, ras#, cas#, a0-a10, ba0 i i 1 -20 20 m a23 any input 0v v in v dd ck0-1, cke0-1, dqmb0-dqmb3 i i 2 -10 10 m a (all other pins not under test = 0v) s0#-s3# i i 3 -5 5 m a output leakage current: dq0-dq31 i oz -20 20 m a23 dqs are disabled; 0v v out v dd output levels: v oh 2.4 C v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol C 0.4 v i dd specifications and conditions (notes: 1, 6, 11, 13) (v dd = +3.3v 0.3v) parameter/condition symbol size -8 -10 units notes operating current: active mode; i dd 1 4mb 270 260 ma 3, 18, burst = 2; read or write; t rc = t rc (min); cas latency = 3 8mb 340 320 19, 28 standby current: power-down mode; i dd 2 4mb 4 4 ma 28 cke = low; all banks idle 8mb 8 8 standby current: active mode; s0#-s3# = high; i dd 3 4mb 70 60 ma 3, 12, cke = high; all banks active after t rcd met; 8mb 140 120 19, 28 no accesses in progress operating current: burst mode; continuous burst; i dd 4 4mb 200 160 ma 3, 18, read or write; all banks active; cas latency = 3 8mb 270 220 19, 28 auto refresh current: t rc = 15.625 m s ; cas latency = 3; i dd 5 4mb 70 60 ma 3, 12, s0#-s3# = high; cke = high 8mb 140 120 18, 19, 28 self refresh current: cke 0.2v i dd 6 4mb 2 2 ma 4 8mb 4 4 max
13 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms sdram component* ac electrical characteristics (notes: 5, 6, 7, 8, 9, 11) ac characteristics -8 -10 parameter symbol min max min max units notes cl = 3 t ac 6 7.5 ns access time from clk (positive edge) cl = 2 t ac 9 9 ns 24 cl = 1 t ac 22 27 ns 24 address hold time t ah 1 1 ns address setup time t as 2 3 ns clk high-level width t ch 3 3.5 ns clk low-level width t cl 3 3.5 ns cl = 3 t ck 8 10 ns 25 clock cycle time cl = 2 t ck 13 15 ns 24, 25 cl = 1 t ck 25 30 ns 25 cke hold time t ckh 1 1 ns cke setup time t cks 2 3 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 2 3 ns data-in hold time t dh 1 1 ns data-in setup time t ds 2 3 ns cl = 3 t hz 6 8 ns 10 data-out high-impedance time cl = 2 t hz 9 10 ns 10 cl = 1 t hz 22 15 ns 10 data-out low-impedance time t lz 1 2 ns data-out hold time t oh 2.5 3 ns active to precharge command period t ras 48 120,000 60 120,000 ns auto refresh and active to active command period t rc 80 90 ns 24 auto refresh period t rcar 80 ns active to read or write delay t rcd 24 30 ns 24 refresh period (4,096 cycles) t ref 64 64 ms precharge command period t rp 24 30 ns 24 active bank a to active bank b command period t rrd 16 20 ns transition time t t 0.3 10 0.3 10 ns 7 write recovery time t wr 1 + 2ns 1 t ck 26 10 10 ns 27 exit self refresh to active command t xsr 80 96 ns 20 capacitance parameter symbol 4mb 8mb units notes input capacitance: a0-a10, ba0, ras#, cas#, we# c i 1 15 25 pf 2 input capacitance: s0#-s3# c i 2 88pf2 input capacitance: dqmb0#-dqmb3# c i 3 815pf2 input capacitance: scl, sa0-sa2 c i 4 66pf2 input capacitance: ck0-ck1, cke0-cke1 c i 5 15 15 pf 2 input/output capacitance: dq0-dq31, sda c io 916pf2 *specifications for the sdram components used on the module. max
14 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms ac functional characteristics (notes: 5, 6, 7, 8, 9, 11) parameter symbol -8 -10 units notes read/write command to read/write command t ccd 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 14 dqm to input data delay t dqd 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 t ck 17 dqm to data high-impedance during reads t dqz 2 2 t ck 17 write command to input data delay t dwd 0 0 t ck 17 data-in to activate command cl = 3 t dal 5 4 t ck 15, 21 cl = 2 t dal 4 3 t ck 15, 21 cl = 1 t dal 3 3 t ck 15, 21 data-in to precharge t dpl 2 1 t ck 16 last data-in to burst stop command t bdl 0 0 t ck 17 last data-in to new read/write command t cdl 1 1 t ck 17 last data-in to precharge command t rdl 1 1 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 t ck 28 data-out to high-impedance from precharge command cl = 3 t roh 3 3 t ck 17 cl = 2 t roh 2 2 t ck 17 cl = 1 t roh 1 1 t ck 17
15 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms serial presence-detect eeprom ac electrical characteristics (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 m s time the bus must be free before a new transition can start t buf 4.7 m s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 m s start condition hold time t hd:sta 4 m s clock high period t high 4 m s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 m s sda and scl rise time t r1 m s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 m s stop condition setup time t su:sto 4.7 m s write cycle time t wrc 10 ms 22 serial presence-detect eeprom dc operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd 0.3 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li C10 m a output leakage current: v out = gnd to v dd i lo C10 m a standby current: i sb C30 m a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i dd C2ma scl clock frequency = 100 khz
16 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a 70 c) is ensured. 6. an initial pause of 100 m s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifica- tion, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: q 50pf 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 12. other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 19. address transitions average one transition every two- clock period. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 125 mhz for -8 and 100 mhz for -10. 22. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to the pull-up resistor, and the eeprom does not respond to its slave address. 23. 4mb module values will be half of those shown. 24. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. 25. the clock frequency must remain constant during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 26. auto precharge mode only. 27. precharge mode only 28. t ck = 10ns for -8, 15ns for -10.
17 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 m s t buf 4.7 m s t dh 300 ns t f 300 ns t hd:dat 0 m s t hd:sta 4 m s spd eeprom symbol min max units t high 4 m s t low 4.7 m s t r1 m s t su:dat 250 ns t su:sta 4.7 m s t su:sto 4.7 m s
18 1, 2 meg x 32 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm14.p65 C rev. 7/99 ? 1999, micron technology, inc. 1, 2 meg x 32 sdram dimms .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ .079 (2.00) r (2x) pin 1 .250 (6.35) typ .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .039 (1.00) r(2x) pin 50 2.850 (72.39) .125 (3.18) max .054 (1.37) .046 (1.17) 1.005 (25.53) 0.995 (25.27) 3.557 (90.34) 3.545 (90.04) .128 (3.25) .118 (3.00) (2x) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 100-pin dimm h-3 100-pin dimm h-4 .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ .079 (2.00) r (2x) pin 1 .250 (6.35) typ .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .039 (1.00) r(2x) pin 50 2.850 (72.39) .157 (4.00) max .054 (1.37) .046 (1.17) 1.005 (25.53) 0.995 (25.27) 3.557 (90.34) 3.545 (90.04) .128 (3.25) .118 (3.00) (2x) 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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